1. Field of the Invention
This invention relates to memory systems and more particularly, to methods and apparatus for controlling the system interface between the system user and the memory.
2. History of the Prior Art
Electrically programmable read only memories (EPROMS) have been used for many different purposes. These memories provide a quick and relatively inexpensive way of furnishing read-only memory. These memories are readily available in arrays up to four megabits. One unfortunate aspect of EPROMs is the difficulty of reprogramming them. In general, an EPROM can only be erased using ultra violet light, which requires removing the EPROM form the system in which the memory is being used. Further, erasure of an EPROM results in erasure of all the data within the memory array of the EPROM.
Because it is often desirable to reprogram read only memory and it is also desirable that this be done without the need to remove the memory from the system, advanced forms of EPROMs have been developed. For example, electrically erasable programmable read only memories (EEPROMs) have been developed which allow the read only memory to be erased at the byte level. This facility allows erasure to be done without removing the memory from the system. It also allows most of the information already in memory to be retained and only the specific information which needs change to be changed. See, for example, U.S. Pat. No. 4,023,158 for a discussion of such EEPROM cells and U.S. Pat. No. 4,266,283 for a discussion of the related circuitry. These memories, however, are always larger physically than are EPROM cells due to the larger cell necessary to implement EEPROM specific functionality. Moreover, they are available only in sizes up to approximately 256K bits.
Recently, a new electrically erasable programmable read only memory called flash EEPROM has been devised. Such a memory array is disclosed in U.S. patent application Ser. No. 667,905, entitled Low Voltage EEPROM Cell, Lai et al, filed Nov. 2, 1984, and assigned to the assignee of the present invention. Flash EEPROM may be electrically erased without removing the memory from the system. Flash EEPROM is available in memory arrays up to two megabits. A difficulty with flash EEPROM, however, is that it operates by applying a high voltage to the source terminals of all of the transistors (cells) within the memory array. Because these source terminals of the cells are all connected by metallic busing in the array, only the entire array may be erased. This requires that the entire array be reprogrammed once it has been erased.
It has been found possible to erase blocks of flash EEPROM by physically separating those blocks during chip layout into groups (blocks) of cells which may be erased together. This reduces the reprogramming effort to some extent but may be used only in a limited manner because the individual blocks of cells must be physically isolated on the silicon in order to allow these blocks to be flash erased separately. The separation requirement significantly increases the size of the silicon chip so that dividing the array into a finer granularity is almost economically impossible. Because large chips cannot be divided into these blocks, a very substantial amount of useful information in memory must be reprogrammed in making any small change in memory.
Thus, even though blocks of flash EEPROM are separated, the reprogramming effort required for flash EEPROM is very extensive. Because of this, there are a great number of chances for one programming flash EEPROM to inadvertently provide incorrect commands to the chip. Of course, such commands may have no effect on the operation of the circuitry or a deleterious effect. Initial efforts with flash EEPROM have disclosed that the programming of such circuitry is so complicated that it is desirable to limit the ability of a programmer to provide programs which may adversely affect the flash EEPROM.